1. Field of the Invention
The present invention relates to a computer motherboard, and more particularly, to a computer motherboard with a control chip having specific data pin and address pin arrangement for fast cache access.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a component layout diagram of a prior art computer motherboard 10. The computer motherboard 10 comprises a four-layer printed circuit board 12, a processor socket 14, two cache data RAMs 16 and 17, a control chip 18, a cache tag RAM 20, a data bus 22 having 64 conductors, and an address bus 24 having 32 conductors.
The four-layer printed circuit board 12 comprises a top layer, a bottom layer, and the two middle layers for connecting power supply and ground. FIG. 1 shows a component layout diagram of the top layer of the motherboard 10. The top layer has top, bottom, left and right sides. The processor socket 14 is installed at the bottom-left portion of the circuit board 12, the cache data RAMs 16 and 17 are installed next to the right side of the processor socket 14, the cache tag RAM 20 is installed next to the top side of the cache data RAM 17, and the control chip 18 is installed next to the top side of the cache data RAM 16 and the top-right side of the processor socket 14.
The pin definition of the processor socket 14 is compatible with the Intel Processor P54C. The processor socket 14 comprises an address section 14a having 32 address pins (A0-A31) positioned at the bottom-left corner of the processor socket 14, and a data section 14b having 64 data pins (D0-D63) positioned at the right side of the processor socket 14. The control chip 18 comprises an address section 18a, processor control section 18b, data section 18c, and cache tag RAM control section 18d arranged from left to right at the bottom side of the control chip 18. The address section 18a comprises 32 address pins (A0-A31), the data section 18c comprises 64 data pins, and each of the processor control section 18b and cache tag RAM control section 18d comprises a plurality of control pins.
The data bus 22 connects the data section 14b at the right side of the processor socket 14, the cache data RAMs 16 and 17, and the data section 18c of the control chip 18. And the address bus 24 connects the address section 14a at the bottom-left corner of the processor socket 14, the cache data RAMs 16 and 17, and the cache tag RAM 20 around the bottom sides of the processor socket 14 and the cache data RAMs 16, 17. In this layout, the length of the address bus 24 between the address section 14a of the processor socket 14 and the cache tag RAM 20 is 9800 mil which causes nearly 2.5 ns signal delay. The length of the address bus 24 between the cache tag RAM 20 and the address section 18a of the control chip 18 is 4200 mil which causes about 1.2 ns signal delay. And the length of the address bus 24 between the address section 14a of the processor socket 14 and the cache data RAM 16 is 8500 mil which results in a roughly 2 ns signal delay. These signal delays do not have too much impact over address data transmission from the processor socket 14 to the cache tag RAM 20 and cache data RAM 16 when the interface speed of the processor socket 14 is running below or around 66 MHz. However, when the interface speed of the processor socket 14 increases to a higher level such as 100 MHz, such signal delays will seriously affect the transmission speed of address data from the processor to the cache tag RAM 20 and to the cache data RAMs 16 and 17 because the allowable transmission time per clock cycle is very limited. In order to reduce these signal delays, each component on the circuit board 12 and the positions of the data bus 22 and the address bus 24 have to be rearranged. However, the pin arrangement of the prior art control chip 18, especially the data section 18c and the address section 18a, makes it very difficult to rearrange the positions of the processor socket 14, control chip 18, cache tag RAM 20, and cache data RAMs 16 and 17 to shorten the length of the address bus 24 between the processor socket 14, control chip 18, cache tag RAM 20, and cache data RAMs 16 and 17.